As devices become smaller and integration density increases, reactive ion etching (RIE) has become a key process in anisotropic etching of semiconductor features. RIE or ion-enhanced etching works by a combination of physical and chemical mechanisms for achieving selectivity and anisotropicity during the etching process. Generally, RIE operates in the milliTorr range and above. Generally, three processes compete with each other during plasma etching; physical bombardment by ions, chemical etching by radicals and ions, and surface passivation by the deposition of passivating films. In some applications, for example, etching high aspect ratio features, high density plasma (HDP) etching having a higher density of ions and operating at lower pressures has been increasingly used in etching high aspect ratio features, for example, having aspect ratios greater than about 3:1.
An increasingly problematical phenomenon in RIE processes is notching, also referred to as micro-trenching, at the base of a polysilicon feature overlying another material, such as an oxide. For example, as device characteristic dimensions decrease, the precise formation of polysilicon gate critical dimensions as well as avoiding damage to the underlying gate dielectric portion is increasingly critical to satisfactory operation of CMOS devices.
Although the reason for notching is not precisely understood and has been a long-standing processing problem, adequate solutions to overcome the problem have to date been less than adequate. Several phenomena including the formation and accumulation of localized charge imbalances during etching are believed to contribute to preferential etching at the base of a polysilicon gate feature. In addition, the simultaneous etching of an underlying oxide layer is believed to create undesirable reactive ion species that contribute to the problem of micro-trenching or undesirable preferential etching at the base of gate electrode feature. While attempts in the prior art to address the problem have including altering etching conditions and chemistries, and schemes have been proposed to reduce charge imbalance accumulation, an adequate solution for etching polysilicon gate structures with required critical dimensions in the absence of micro-trenching remains a problem to be overcome.
In addition, the problem of micro-trenching is particularly problematical where both NMOS and PMOS gate electrode structures are formed in parallel in a single RIE etching process. One particular micro-trenching phenomenon involves the formation of a ‘notch’ (decrease in the gate electrode width) at the base of the polysilicon electrode where the degree of notching may depend in part on the dopant type of the polysilicon. In addition, damage to the underlying gate dielectric can occur in overetching processes. Etching defects including notches adversely affect critical electrical properties of CMOS devices including decreased dielectric breakdown strength, Voltage threshold variations, and current leakage.
There is therefore a need in the semiconductor processing art to develop an improved method for plasma assisted etching of polysilicon including gate electrodes to achieve improved etching profiles while avoiding the formation of preferential etching defects to thereby improve semiconductor device reliability and yield.
It is therefore an object of the invention to provide an improved method for plasma assisted etching of polysilicon including gate electrodes to achieve improved etching profiles while avoiding the formation of preferential etching defects to thereby improve semiconductor device reliability and yield, while overcoming other shortcomings and deficiencies of the prior art.